A product-sum operation circuit that performs a matrix product operation has been known (See, for example, Japanese Laid-Open Patent Publication No. 2009-245296). A predetermined number of multipliers execute in parallel the integration of each row vector constituted by a group of a predetermined number of elements in a row direction among elements of a first matrix and each column vector constituted by a group of a predetermined number of elements in a column direction among elements of a second matrix. An adder for multipliers acquires and adds multiplication results of the multipliers at the next stage of the multipliers, of which number is the same as that of the elements. An adder for adders acquires and adds the addition result of the adder for the multipliers at next stage of the adder for the multipliers. A latency counter measures a latency of an adder for the adder placed at the last stage. The variable counter counts each time when the latency counter measures latency of the adder for the adders at the last stage and outputs a signal indicating that an operation result of the matrix product may be acquired when counting is performed until a count value reaches a predetermined number of accumulation. The variable counter setting unit sets a count value of the variable counter.
Further, the matrix operation device has been known (See, for example, Japanese Laid-Open Patent Publication H10-63647). The matrix operation device divides and stores data of all elements of a matrix required to be operated in a plurality of divided storage memory of matrix data and simultaneously outputs the necessary data from the plurality of divided storage memory of matrix data using the reading unit according to the decoding results of a decoder. Also, the matrix operation device transfers data to the product-sum operation unit through the selector unit to perform the product-sum operation and outputs the operation result, and also records the operation result in the divided storage memory of matrix data through a recording unit.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2009-245296 and Japanese Laid-Open Patent Publication No. H10-63647.
It is necessary to calculate a large quantity of products of complex matrices in a signal processing for wireless communication. Since a lot of multipliers are needed for obtaining the product of the complex matrix, the circuit area and power consumption increase. Further, inconsistent number of rows and columns of a matrix for which a product is to be obtained causes an increase of the circuit area. For example, when intending to calculate a channel capacity for a case where the number of transceiver antennas is 4 (four), it is necessary to obtain the products of matrices having various different sizes, for example, a product of a matrix with 4 rows and 4 columns and another matrix with 4 rows and 4 columns, or a product of a matrix with 3 rows and 4 columns and a matrix with 4 rows and 3 columns.
In LTE (Long Term Evolution)-Advanced communication standard, the number of transceiver antennas may be as many as 8 (eight) at maximum and thus it is necessary to obtain more number of products of matrices which have different sizes than ever before, so that an amount of calculation itself increases.
The simplest solution to the calculation is to mount a calculation circuit of a product of matrixes having different sizes in hardware. However, in this case, an operation unit that is not being activated may exist, which results in an increase of a circuit area due to existence of an unnecessary operation unit.
The present disclosure intends to provide the product-sum operation circuit and the product-sum operation system that may perform a product operation of matrices having various sizes at a smaller circuit area.